1. Field of Invention
The invention relates generally to noise reduction in phase locked loops (PLL) which employ ring type voltage controlled oscillators (VCO), and more specifically to apparatuses and methods for phase noise reduction in phase locked loops employing true fractional divide capability.
2. Art Background
Phase locked loops are used in a wide range of applications such as clock generation, clock alignment, deskewing, jitter reduction, clock distribution, frequency synthesis, etc. Phase noise arises when state transitions of a clock signal depart from the ideal instances causing narrower timing margins and degradation of system performance. This can present a problem.
Electronic devices such as computers, mobile phones, tablets, network equipment, communication channels, etc. often have a variety of oscillators operating at different frequencies. “Clean” oscillators are those based on vibration of a crystal. Crystal oscillators exhibit very stable vibration characteristics which result in low phase noise. Crystal oscillators of arbitrary frequency are impractical because quartz crystals have limited frequency range (kHz to MHz range) and high frequency crystals are expensive. An example of a crystal-less oscillator is a ring voltage controlled oscillator (VCO) constructed with an odd number of inverters or related devices. Ring VCOs are susceptible to the accumulation of phase noise due to thermal and flicker noise in the inverters or in the other electronic devices that are used in the ring, such as NOR gates, etc. The accumulation of phase noise over many cycles in a ring VCO leads to phase noise which can become unacceptably high for a given application, thereby rendering the low cost ring VCO unsuited for the given application. This can present a problem.